Along with the miniaturization of semiconductor devices, there has been an increase in unpredictable defects for which it is impossible to specify the positions in advance so that it has become a problem that the time that it takes to launch production due to the inspection of the defects is increasing. As a result, in order to aim for improvement in the efficiency of defect detection, there is a need to implement pattern defect detection on the full face, or a size close thereto, of a single shot within a wafer.
As a technique therefor, there is known a charged particle beam device that acquires a plurality of images of small regions (with widths of several microns) and forms one synthesized image by joining these together (may be referred to as panoramization, hereinafter) to perform defect detection or measurement.
In Patent Literature 1, a technique is disclosed to carry out panorama synthesis of semiconductor circuit patterns while easiness of matching is enhanced by analyzing design data of patterns in a stage prior to capturing images of patterns and carrying out image capturing of the patterns so that patterns for which it is easy to specify synthesized positions of images fall in the overlapping regions between the images subject to synthesis.
Besides, techniques of evaluating the quality of a pattern by measuring not only the width of the pattern but also the two-dimensional profile of the pattern have gradually been adopted. Since pattern edges displayed in images obtained with an electron microscope or the like have a certain width due to the edge effect and the profile thereof is difficult to specify, pattern edge contouring technology is known as a technique for carrying out accurate two-dimensional measurements. Contouring is technology that, on the basis of the brightness distribution of the pattern edges, narrows the edge portions into thin lines. In Patent Literature 2, there is described technology that panoramizes pattern information converted into narrow lines.